A latch is a basic component of digital circuitry within many digital designs. While latches typically operate with a high rate of reliability, these components occasionally function improperly.
For example, in MOS integrated circuits, the state of a logic circuit is determined by the charge stored on multiple capacitors. In MOS VLSI designs where gate size is small, transient activities may cause a latch to fail. For example, when a latch in such an integrated circuit is hit by an alpha particle or a gamma ray, the charge on the associated capacitor may change, causing the latch to fail temporarily.
Other failures may be caused by problems in the manufacturing process. Process variations may cause non-linear timing variations, leading to latent hazard conditions. Errors of this type tend to be intermittent and may be difficult to detect. Errors in device assembly such as broken connector wires or foreign matter in the circuit may also result in disfunctional circuitry.
Another potential cause of improper latch operation is metal migration. This may occur when a circuit is operated at too high a temperature causing the metalization layers of the integrated circuit to flow. Broken conduction paths and increased metal resistance caused by this effect may result in intermittent or permanent failures.
Concerns for proper latch operation extend to many configurations. For example, it may be desirable to have a latch type device in which signal changes at the output terminal are effectively isolated from signal changes at the input terminal. Such a scheme is useful where an output of a first latch is connected to the input of a second latch, and where a change of state in the first latch should not propagate through to the second latch.
A type of latch which satisfies these constraints is a master-slave latch. In a master slave configuration, two latches are coupled together, with the output of one tied to the input of the other. This creates a two stage configuration. To reach the output of the second stage, data is placed into the first stage (called the master), responsive to a first clock signal. Upon reaching the first stage output, the data value is transferred to the second stage (called the slave) responsive to a second clock signal. The first and second clock signals may be separate or they may be respectively different transitions of a single clock signal.
U.S. Pat. No. 4,493,077 to Agrawal relates to an integrated circuit which can be reconfigured to step test data through its internal components.
U.S. Pat. No. 4,513,418 to Bardell relates to a shift register based upon level sensitive scan design which can perform signature analysis as a means of self-test.
U.S. Pat. No. 4,554,664 to Schultz relates to a latch cell based upon level senstive scan design. A static functional latch and a dynamic test latch are included.